A demand for enhancing information processing performance to a microprocessor has been increased from year to year, and an enhancement in an operating frequency of the microprocessor has been executed in order to satisfy the demand. In a current semiconductor integrated circuit (LSI), moreover, most of necessary system functions can be integrated in one chip with the progress of a semiconductor process technology. For example, an audio processing IP (Intellectual Property) and an image processing IP can be integrated together with a CPU (central processing unit). Such a semiconductor chip will be referred to as an “SoC (System-on-a-Chip)”. Thus, an integrating force is enhanced so that the SoC mounting a plurality of CPUs in the LSI can also be obtained. Consequently, it is possible to implement a parallel processing on a chip.
There has been known an LSI in which a plurality of CPU cores is provided in an SoC (for example, Patent Document 1). Two microprocessors have different instruction control methods from each other. A core for a high speed operation is set to be an RISC (Reduced Instruction Set Computer) and a CPU core for a low speed operation is set to be a CISC (Complex Instruction Set Computer).
Moreover, there has been known an LSI including two CPU cores to employ microarchitectures having different numbers of pipeline stages (fore example, see Patent Document 2). In the LSI, a CPU core to be operated at a high speed is operated at a high source voltage on a large scale and a CPU core to be operated at a low speed is operated by a CPU core having a low source voltage on a small scale in a small number of pipeline stages.
Furthermore, there has been known an LSI including two CPU cores having different performances from each other due to a deference in a logical synthesis (for example, Patent Document 3). In the LSI, the CPU core to be operated at a high speed is constituted by a transistor having a small threshold and the CPU core to be operated at a low speed is constituted by a transistor having a great threshold.
[Patent Document 1] JP-A-7-325788 Publication
[Patent Document 2] JP-A-2002-215597 Publication
[Patent Document 3] JP-A-2002-288150 Publication